Description: Logic Synthesis and Verification Algorithms Please note: this item is printed on demand and will take extra time before it can be dispatched to you (up to 20 working days). Author(s): Gary D. Hachtel, Fabio Somenzi Format: Paperback Publisher: Springer-Verlag New York Inc., United States Imprint: Springer-Verlag New York Inc. ISBN-13: 9781475770360, 978-1475770360 Synopsis Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.
Price: 59.98 GBP
Location: Aldershot
End Time: 2024-12-07T09:25:06.000Z
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Book Title: Logic Synthesis and Verification Algorithms
Number of Pages: 564 Pages
Language: English
Publication Name: Logic Synthesis and Verification Algorithms
Publisher: Springer-Verlag New York Inc.
Publication Year: 2013
Subject: Computer Science, Mathematics, Physics
Item Height: 254 mm
Item Weight: 1126 g
Type: Textbook
Author: Gary D. Hachtel, Fabio Somenzi
Subject Area: Electrical Engineering
Item Width: 178 mm
Format: Paperback
